Static random access memory (SRAM) is often implemented using a bistable transistor flip-flop or latching circuit. The word “static” indicates that the memory retains its contents as long as power remains applied. “Random access” means that locations in the memory can be written to or read from in any order, regardless of the memory location that was accessed last.
SRAMs offer advantages including reliability and fast reading and writing of the stored data. The data retained in the SRAM cell is volatile. Interruption of the power supply source causes loss of the data in the SRAM cell.
A non-volatile SRAM (nvSRAM) includes an SRAM cell coupled with a nonvolatile memory cell. The nonvolatile cell may be implemented in different ways, for example using a Silicon Oxide Nitride Oxide Silicon (SONOS) transistor or a floating gate transistor with stored charge that modifies the transistor's voltage threshold. Data stored in a nonvolatile memory cell is not lost upon interruption of power.
FIG. 1 illustrates an embodiment of a conventional nvSRAM cell. The cell 100 comprises a volatile cell 106 and nonvolatile cell 101. Volatile charge is stored in the volatile cell 106 at nodes 118 and 116. Trigates 102, 104 of the nonvolatile cell 101 store nonvolatile charge via SONOS transistors 110, 112.
The nvSRAM device 100 is illustrated as having a single nvSRAM memory cell (in this case, the single SRAM 106 and a single non-volatile memory cell 101), but it should be appreciated that an nvSRAM device typically includes a plurality of nvSRAM cells that are integrated with a controller onto a semiconductor chip to form an array. Generally, an nvSRAM cell 100 comprises transistors, capacitors, and resistors. Not all elements are necessarily illustrated due to being unnecessary for an explanation or understanding of the circuit and its operation. It should be appreciated that various types of transistors, such as n-channel and p-channel FETs, and combinations of different types of transistors, may be utilized.
The SRAM cell 106 is capable, as long as power is being provided, of receiving a bit of data from an exterior environment, retaining the bit of data, and transmitting the bit of data back to the exterior environment. If power is removed from the SRAM cell 106, the SRAM cell 106 will lose the bit of data. The nonvolatile cell 101 prevents loss of the bit of data by providing the capability to receive the bit of data from the SRAM cell 106, retain the bit of data in the absence of power being provided to the SRAM cell 106, and return the bit of data to the SRAM cell 106 when power is restored. Returning a bit of data from the NV cell 101 to the SRAM cell 106 is referred to as a RECALL operation.
FIG. 1 illustrates a six transistor SRAM cell 106. The SRAM cell 106 typically has three states: standby, writing and reading. WRITE and READ procedures for an SRAM cell 106 are well known and will not be described herein.
In the standby state, the circuit is idle. The word line WL is not asserted and so transistors 120, 122 disconnect the SRAM cell 106 from the bit lines BT and BC. The first cross coupled inverter formed by transistors 124, 126 and the second cross coupled inverter formed by transistors 128, 130 continue to reinforce each other and the data stored in the cell 106 remains at nodes 116 and 118 remains stable.
The nonvolatile portion 101 includes SONOS FETs 110, 112 for nonvolatile storage of the state of the SRAM cell 106. It should be appreciated that the SONOS FETs 110, 112 can be replaced with other types of nonvolatile storage elements, such as silicon nitride oxide semiconductor (SNOS) transistors, floating gate transistors, ferroelectric transistors, and capacitors to name a few.
The FETs 114 function to connect the nonvolatile portion 101 to the volatile portion 106 during STORE and RECALL operations and to otherwise disconnect the nonvolatile portion 101 from the volatile portion 106. The FETs 108 function to connect the nonvolatile portion 101 to VCCT during a RECALL operation and to disconnect the nonvolatile portion 101 from VCCT during a STORE operation. The FETs 108 are controlled by a VRCL signal that is applied to the gates of the FETs. The control signals on the VRCL, VSE, VSTR and word lines WL are provided by a device control unit (not shown).
The transfer of data from the volatile section 106 to the non-volatile section 101, i.e. a STORE operation, takes place in two steps, during which the word line, WL, is OFF (e.g. 0V). During the first (ERASE) portion of the STORE operation, nonvolatile control lines VSTR and VRCL are OFF (e.g., 0V). By pumping a voltage on VSE, the gates of SONOS transistors 110, 112 are reduced to a relatively large negative voltage (e.g., −10V) sufficient to positively charge the nitride dielectric through direct tunneling across the tunnel oxide. The erase portion of the STORE is completed by discharging VSE back to ground.
During the second (PROGRAM) portion of the STORE operation, the state of the volatile cell 106 is stored by the nonvolatile portion 101. Assume the SRAM cell 106 stores a logic “1”. This means node 118 (i.e., DT) is HIGH (e.g., 1.8V) and node 116 (i.e., DC) is LOW (e.g., 0V). A programming signal of approximately 10V is applied on VSE. A voltage higher than Vt of transistors 114 and 115 is applied to VSTR. Transistor 114 has gate and source voltages both HIGH and is thus cutoff. Transistor 115 has a HIGH gate voltage and a LOW source voltage and is thus ON. The SONOS transistor 112 corresponding to node 116 (i.e, DC) gets programmed as electrons tunnel into the nitride and get stored, thus raising the threshold voltage of this SONOS transistor 112. The SONOS transistor 110 on the DT side (i.e., node 118) of the SRAM cell 106 stays erased.
A RECALL operation begins by clearing the existing SRAM data, first by discharging the bit lines, BT and BC to ground, clamping VCCI to VSSI and then by turning ON the word line, WL. The volatile bit nodes 118 and 116 are discharged to ground. WL is then turned OFF. VSTR and VRCL are turned on, providing a charging path from VCCT to the volatile bit nodes 118 and 116 through the nonvolatile section 101. VSE is set LOW. Assuming the last STORE operation left SONOS transistor 110 erased and SONOS transistor 112 programmed (see the description of STORE, supra), and assuming that the erase threshold is −1V and the program threshold is +1V, the SONOS transistor 110 will conduct current while the SONOS transistor 112 will not because its gate voltage is below its threshold voltage VT. Node 118 charges up HIGH, while node 116 remains LOW, thereby recalling the state retained by the last STORE operation. The RECALL operation is completed by powering up the SRAM and returning all control lines to their default states.